Many microchip designs are crafted in similar processes. At the beginning stage of a typical design process, or "front end", a logic designer uses a Very High Speed Integrated Circuits (VHSIC) Design Language (VHDL) to generate a behavioral description of the chip or chip element. This behavioral description is abstracted to a fairly high level, such as the bus level, and lower-level constructs, such as pins and individual nets, are not present in the front end behavioral description.
The VHDL behavioral model then proceeds through a behavioral synthesizer to create a Register Transfer Language ("RTL") VIM (VLSI Integrated Model) netlist. This netlist is less abstract that the VHDL behavioral description, and represents, rather than buses, the individual wires connecting logic boxes. The VHDL behavioral description also goes through a logical synthesis, which creates a physical design ("PD") VIM netlist that is forwarded to the physical designer. The physical designer is involved in the "back end" of the design process, where low-level design decisions are made.
The physical designer typically runs the PD VIM netlist through physical design tools, which places and routes the ultimate, low-level physical components of the chip, such as pins 1 and wires. The design is ultimately sent to a foundry, where the masks for chip processing are finalized. Any changes to the physical chip layout are described in an Engineering Change Order (ECO).
Unfortunately, design flaws often come to light late in the logic verification, physical design, or manufacturing process. Traditionally, there has been no efficient manner of making changes to the chip design once the layout of the thousands of wires has been created at the back end of the chip design process. As stated above, an ECO must be generated in order to make a change to the PD VIM. What is desired is a manner of automatically formatting ECO language, suitable for processing by an Electronic Design Automation (EDA) tool in order to specify metal-only design changes to complex hardware data-paths through changes in the netlist. Such automatic formatting of an ECO would ensure that the source VHDL language does not need resynthesizing in order to change the design. Dispensing with the need to resynthesize VHDL in order to implement design changes allows the designers to avoid the expensive and time consuming prospect of repeating the entire engineering design cycle. As an alternative to resynthesis, the prior art requires the logic designer to identify which of the thousands of wires and pins must be re-routed and re-placed. This process is not only tedious, and time-consuming, but is also error-prone. The present invention eliminates the need to perform either of these prior art methods for implementing relatively late design changes.